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Stupid idea for acceleration card and AROS

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I've been playing for a while with the st-microelectronics line of arm processors, namely the stm32f7-series.

Microcontrollers have come a long way from the pic16f84 when I was first stunned by them.

The stm32f7 has cortex-m7 core and go up to 216MHz. I've been long waiting for it's successor the stm32h7 that goes 400MHz. Finally they've released it!

These st micros have an FMC, flexible memory controller and they directly connect to multiple memory interfaces. SDRAM, SRAM, QSPI etc.

Using the m68k cpu emulator from MAME there could be a software cpu emulator card for the Amiga. (or without binary compatible a thumb2 native card)

https://github.com/kstenerud/Musashi

With bit of glue logic and tweaking (using the FMC NAND interface or something else) the stm(f/h)7 could be used on a accelerator card. STM32F/H can address upto 512Mbytes of SDRAM and same amount of SRAM and what else.

I've butchered the AROS code to distinguish between arm and thumb(2) code but I'm unable to make a gcc crosscompiler for AROS using it.

I've been using the ARM embedded compiler provided by ARM limited when coding for different ST boards (stm32f7-discovery and Waveshare 746)

My Linux gcc (Fedora 27) is unable to compile the 6.3.0 gcc as the code neened to compile would require the use of -fpermissive and I haven't yeat looked for where to put it.

I have a sinister plan in my mind that if AROS is ever to be able to use the said mcu then I'd stole it and use it on my never ending CNC project and control my CNC Bridgeport, or 3D printer...

More on that on my channel: https://www.youtube.com/channel/UCGAgv ... OOgPlg?view_as=subscriber

Posted on: 1/27 8:06

Edited by DizzyOfCRN on 2018/1/27 8:49:55
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Re: Stupid idea for acceleration card and AROS

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That sounds remarkable. Could it be be used to make something like this?

Cheers,
Nigel.

Posted on: 1/27 15:23
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Re: Stupid idea for acceleration card and AROS

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Interesting, indeed! Thanks for sharing!

Posted on: 1/27 23:02
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Re: Stupid idea for acceleration card and AROS

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Quote:

ntromans wrote:
That sounds remarkable. Could it be be used to make something like this?

Cheers,
Nigel.


I need to have an FPGA for the CNC board as there are many quadrature signals to count. If there wasn't a need for so many encoders it could be done with the timers inside the stm32f/h.

x,y,z,a,b,c,s and handwheel have encoders. Well I only need x,y,z,(a/b/c),s and handwheel, but if there are pins still left on the fpga then why not implement it fully.

The stm32f/h have peripherals for audio, video, ethernet, usb(fs/hs), dac, adc and many others.

stm32f7 can output video to the resolution that the memory bus allows, video controller share the same bus with cpu.

stm32f7 can clock sdram at 100MHz and the stm32h7 at a rate of 200Mhz. stm32h7 should be able to go higher resolution.

I've tested Waveshare board at 800x480 resolution and it works well. The panel I used is 18-bit (R,G and B each have 6 bits)

Posted on: 1/28 2:43
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Re: Stupid idea for acceleration card and AROS

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I was thinking an FPGA board would be needed for I/O, but it seems that this board already has all of that including some robotics/datalogging interface lines. If, due to your efforts, AROS will run on this board, could this be the 'standardised' hardware we were talking about over on the other thread (sort of AROS's answer to the RPi)? Do you have any good links to to information (prices etc.) on this?

Cheers,
Nigel.

Posted on: 1/28 5:55
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Re: Stupid idea for acceleration card and AROS

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Quote:

ntromans wrote:
I was thinking an FPGA board would be needed for I/O, but it seems that this board already has all of that including some robotics/datalogging interface lines. If, due to your efforts, AROS will run on this board, could this be the 'standardised' hardware we were talking about over on the other thread (sort of AROS's answer to the RPi)? Do you have any good links to to information (prices etc.) on this?

Cheers,
Nigel.

These st devices are just small embedded controllers. Video is not much more than a plain frame buffer, not much competition against more mature SoC's with their GPU's and other stuff.

Price wise these boards are in the 20 to 100€. Cost of the stm32f/h7 mcu is 10 to 15€ in quantities of one.

I managed to build AROS cross compiler for the thumb2 set, well I think...

My hosts gcc is version 7.2.1 and it won't build gcc 6.3.0 which I need at least. With bit of patching the AROS diff file I think I managed to get something...

diff -ruN gcc-6.3.0/gcc/ubsan.c gcc-6.3.0.aros/gcc/ubsan.c
--- gcc-6.3.0/gcc/ubsan.c
+++ gcc-6.3.0.aros/gcc/ubsan.c
@@ -1471,+1471,@@

    
expanded_location xloc expand_location (loc);
    if (
xloc.file == NULL || strncmp (xloc.file"1"2) == 0
-      || xloc.file == '' || xloc.file[0] == 'xff'
(plus here)      || xloc.file[0] == '' || xloc.file[0] == 'xff'
       
|| xloc.file[1] == 'xff')
      return 
false;


There was also need to patch the multilib part of AROS gcc diff. I just substituted the whole t-aros file with t-mlibs from gcc sources here https://github.com/PaulStoffregen/ARM_Toolchain_2014q3_Source

I also used Binutils 2.27

[dizzy@linux ~]$ arm-aros-gcc -v
Using built-in specs.
COLLECT_GCC=arm-aros-gcc
COLLECT_LTO_WRAPPER=/home/dizzy/AROS.arm/libexec/gcc/arm-aros/6.3.0/lto-wrapper
Target: arm-aros
Configured with: /home/dizzy/AROS.stm32f7_discovery_crosstools/bin/linux-x86_64/Ports/host/gcc/gcc-6.3.0/configure --prefix=/home/dizzy/AROS.arm --target=arm-aros --with-arch=armv7e-m --with-float=hard --with-fpu=fpv5-sp-d16 --with-mode=thumb --disable-libunwind-exceptions --with-sysroot=/home/dizzy/AROS.stm32f7_discovery_crosstools/bin/stm32f7_discovery-arm/AROS/Developer --with-native-system-header-dir=/include --bindir=/home/dizzy/AROS.arm --libdir=/home/dizzy/AROS.arm/lib --enable-languages=c,c++ --enable-long-long --enable-version-specific-runtime-libs --enable-frame-pointer --with-isl=/home/dizzy/AROS.arm --disable-isl-version-check --disable-bootstrap --disable-sjlj-exceptions --disable-tls --disable-plugins --disable-nls --disable-libssp --disable-libstdcxx-pch --disable-build-with-cxx --disable-build-poststage1-with-cxx
Thread model: posix
gcc version 6.3.0 (GCC)

[dizzy@linux ~]$ arm-aros-as -version
GNU assembler (GNU Binutils) 2.27
Copyright (C) 2016 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `arm-aros'.

EDIT:

Not quite there yeat, aros-gcc produces double precision float opcodes or softfpu. stm32h7 has single and double precision but the stmf7 has only single precision.

EDIT:

Oh, my bad... Compiler defaults hard coded decimals into double's, needed to cast them to floats.

Posted on: 1/29 5:09

Edited by DizzyOfCRN on 2018/1/29 5:36:57
Edited by DizzyOfCRN on 2018/1/29 7:02:31
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Re: Stupid idea for acceleration card and AROS

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The price point would seem ideal, and for that sort of money you wouldn't be expecting anthing fancy like 3D. What do you think the chances would be that AROS could support it for audio, ethernet and USB?

Cheers,
Nigel.

Posted on: 1/29 9:42
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Re: Stupid idea for acceleration card and AROS

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Quote:

ntromans wrote:
The price point would seem ideal, and for that sort of money you wouldn't be expecting anthing fancy like 3D. What do you think the chances would be that AROS could support it for audio, ethernet and USB?

Cheers,
Nigel.


Bit early on that... Still trying to figure out how to make AROS build system not to build the arm-aeabi lib. (or build it but with many ifdefs. Unified syntax comes also in the play)

Cortex-m7 has SDIV/UDIV as per thumb2 instruction set.

http://infocenter.arm.com/help/index. ... oc.dui0646b/BABFADHJ.html

Posted on: 1/29 11:56
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Re: Stupid idea for acceleration card and AROS

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Thanks. Please do keep us informed of developments with this, I think it looks to have great promise!

Cheers,
Nigel.

Posted on: 1/30 10:05
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Re: Stupid idea for acceleration card and AROS

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GCC 6.3.0 produced bad code for the cortex-m7 if-then instructions. (IT blocks) GCC ARM embedded has different code for the instruction than what is on 6.3.0

With a bit of patching I managed to make this:

[dizzy@linux AROS.arm_730]$ ./arm-aros-gcc --verbose
Using built-in specs.
COLLECT_GCC=./arm-aros-gcc
COLLECT_LTO_WRAPPER=/home/dizzy/AROS.arm_730/libexec/gcc/arm-aros/7.3.0/lto-wrapper
Target: arm-aros
Configured with: /home/dizzy/AROS.stm32f7_discovery_crosstools_730/bin/linux-x86_64/Ports/host/gcc/gcc-7.3.0/configure --prefix=/home/dizzy/AROS.arm_730 --target=arm-aros --with-arch=armv7e-m --with-float=hard --with-fpu=fpv5-sp-d16 --with-mode=thumb --disable-libunwind-exceptions --with-sysroot=/home/dizzy/AROS.stm32f7_discovery_crosstools_730/bin/stm32f7_discovery-arm/AROS/Developer --with-native-system-header-dir=/include --bindir=/home/dizzy/AROS.arm_730 --libdir=/home/dizzy/AROS.arm_730/lib --enable-languages=c --enable-long-long --enable-version-specific-runtime-libs --enable-frame-pointer --with-isl=/home/dizzy/AROS.arm_730 --disable-isl-version-check --disable-bootstrap --disable-sjlj-exceptions --disable-tls --disable-plugins --disable-nls --disable-libssp --disable-libstdcxx-pch --disable-build-with-cxx --disable-build-poststage1-with-cxx
Thread model: posix
gcc version 7.3.0 (GCC)

Which is untested at the moment

EDIT:

Tested the GCC 7.3.0 compiler. It won't build with c++ enabled as it wants to start building libquadmath which it fails to build. 128 bit floats... ?

GCC 7.3.0 has more strict C, it fails to build developer/debug/test/clib/snprintf.c

/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./snprintf.c:32:11: error: 'snprintf' output truncated before the last format character [-Werror=format-truncation=]
TEST((snprintf(buf, BUFSIZE, "%s", TESTSTRING3) == strlen(TESTSTRING3)));
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./test.h:15:14: note: in definition of macro 'TEST'
if(!(x)) \
^
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./snprintf.c:32:11: note: 'snprintf' output 11 bytes into a destination of size 10
TEST((snprintf(buf, BUFSIZE, "%s", TESTSTRING3) == strlen(TESTSTRING3)));
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./test.h:15:14: note: in definition of macro 'TEST'
if(!(x)) \
^
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./snprintf.c:37:11: error: '%s' directive output truncated writing 18 bytes into a region of size 10 [-Werror=format-truncation=]
TEST((snprintf(buf, BUFSIZE, "%s", TESTSTRING4) == strlen(TESTSTRING4)));
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./test.h:15:14: note: in definition of macro 'TEST'
if(!(x)) \
^
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./snprintf.c:37:11: note: 'snprintf' output 19 bytes into a destination of size 10
TEST((snprintf(buf, BUFSIZE, "%s", TESTSTRING4) == strlen(TESTSTRING4)));
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/dizzy/AROS_Vanilla/developer/debug/test/clib/./test.h:15:14: note: in definition of macro 'TEST'
if(!(x)) \
^
cc1: all warnings being treated as errors

Here's bit more info about it:
https://bugzilla.redhat.com/show_bug.cgi?id=1431678

"In cases when truncation is expected the caller typically checks the return value from the function and handles it somehow (e.g., by branching on it). In those cases the warning is not issued."

Looking at the snprintf AROS testcase the return value needs to be checked in some specific way for GCC 7.3.0 as it is being checked in the snprintf test case?

EDIT:

I also had to copy the libgcc.a from gcc version 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496] to get the needed aeabi functions for the c compiler to work.

EDIT:

Here's the diff file: https://www.dropbox.com/s/hgwp5l689jshibq/gcc-7.3.0-aros.diff?dl=0

Posted on: 2/2 2:59

Edited by DizzyOfCRN on 2018/2/2 13:49:42
Edited by DizzyOfCRN on 2018/2/2 13:52:48
Edited by DizzyOfCRN on 2018/2/2 14:04:25
Edited by DizzyOfCRN on 2018/2/2 14:05:12
Edited by DizzyOfCRN on 2018/2/2 14:52:29
Edited by DizzyOfCRN on 2018/2/2 14:53:19
Edited by DizzyOfCRN on 2018/2/2 14:56:13
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